The present invention relates to a semiconductor device for use in amplification of power and, more particularly, to the structure of a power transistor designed to enhance reverse-bias breakdown endurance so as to extend the area of safe operation (ASO).
For enhancing the reverse-bias breakdown endurance (Ersb) of a power transistor, there are generally known the following techniques. A first technique includes enlarging a chip size and increasing the number of transistor unit cells, to reduce the current density per unit cell. A second possible technique is widening the base of each unit cell immediately below its emitter, or widening its collector layer of a low impurity concentration. Then, upon application of a reverse bias between the base and emitter, expanding the electron flow between the collector and emitter while reducing the electron density in the juction, thereby preventing localized flow of the electrons. A third known technique uses increasing the impurity concentration in the base or that in the collector layer of a low impurity concentration. According to the techniques mentioned above, occurrence of any hot spot can be avoided to prevent secondary breakdown, hence achieving some improvement in the reverse-bias breakdown endurance.
However, the first method that enlarges the chip size naturally brings about an increase of the production cost. In the second method, some deterioration is unavoidable with regard to the current amplification characteristics due to the fact that principally the collector current is decreased at the maximal current amplification factor. As for the third method which raises the impurity concentration in the collector layer, there exist disadvantages including reduction of the voltage withstanding capability. It has been customary heretofore that, because of a mutually contrary relationship existing between the reverse-bias breakdown endurance and the current characteristic or withstanding voltage characteristic, the power transistor is designed to be optimal with trade off of such two characteristics.
It is well known that the electric characteristics of a power transistor are associated with a peripheral length (l.sub.E) of its emitter. For example, one important electric characteristic is the relationship among the peripheral length (l.sub.E) of an emitter, a collector-emitter saturation voltage Vce (SAT) and a reduction (value n) induced in a current amplification factor h.sub.fe at a flow of large current. In such relationship, both the saturation voltage Vce (SAT) and the value n are sequentially reduced in accordance with an increase of the length l.sub.E to enhance the characteristic to a certain extent until arrival of l.sub.E at a predetermined value l.sub.EO. However, posterior to such point, the characteristic reaches saturation and therefore fails to be improved despite any further increase of l.sub.E.
Meanwhile, with regard to the relationship between the width L.sub.E of an emitter and the peripheral length l.sub.E thereof, the integration density of transistor unit cells can be raised in the case of a mesh emitter type pattern to increase the peripheral length l.sub.E in proportion to a reduction of the emitter width L.sub.E with the chip size remaining unchanged. However, as described above, no enhancement is attainable in the electric characteristics by decreasing the emitter width L.sub.E and increasing the peripheral length l.sub.E up to any region beyond the aforesaid predetermined value l.sub.EO. Since a sufficient peripheral length l.sub.E is obtainable with an emitter width L.sub.E of 70 microns or more, it has been considered meaningless to reduce the emitter width further than the above value in view of the electric characteristics. As for the reverse-bias breakdown endurance Ersb, although its value can be augmented by narrowing the emitter width L.sub.E and increasing its peripheral length l.sub.E it has been believed that, as represented by the characteristic (a) in FIG. 3, the improvement attainable is merely slight on the known extension line. Furthermore, if the emitter width is reduced for achieving a high yield rate in the process of production, it becomes necessary to render the pattern finer to eventually bring about deterioration of the yield rate on the contrary. Therefore, in the conventional design, it has been customary to set the emitter width L.sub.E at a value suited for obtaining an adequate emitter peripheral length l.sub.E which is slightly greater than the aforesaid predetermined value l.sub.EO. For the reasons given above, the emitter width of the ordinary mesh emitter type power transistor in general use today is so established as to range from 70 to 100 microns or more, and any emitter width narrower than that has never been adopted in design.